发明名称 STACK PACKAGE AND METHOD FOR FABRICATING OF THE SAME
摘要 A stacked package and a method of manufacturing the same are provided, which can secure the junction simplicity and junction reliability by using the reflow process. Two or more semiconductor chips are stacked in the stacked package(100). A plurality of via holes(V) are equipped in order to be mutually detached from each other inside the semiconductor chip. The metal layer(120) is reclaimed inside the via hole so that the groove can be built from the lower-part of the semiconductor chip in a certain depth. The connection terminal(130) is adhered on the metal layer of the semiconductor chip upper face. The connection terminal is inserted within the groove of the semiconductor chip lower-part placed in the top and performs the electrical connection. The connection terminal is made of the conductive polymer or solder.
申请公布号 KR20090076357(A) 申请公布日期 2009.07.13
申请号 KR20080002254 申请日期 2008.01.08
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, SUNG MIN;PARK, CHANG JUN;HAN, KWON WHAN;KIM, SEONG CHEOL;CHOI, HYEONG SEOK;LEE, HA NA
分类号 H01L23/12 主分类号 H01L23/12
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