| 摘要 |
#CMT# #/CMT# The module (100) has buffer devices (108) comprising a symmetrical circuit design such that the devices are independent of each other in longitudinal direction of a printed board (102). The buffer devices comprise separate left and right signal ports for buffered address, command and clock signals, to transfer the signals over a left side and/or right side unbranched fly-by-signal line loop (114) corresponding to signal ports of memory devices (106) e.g. double-data-rate three synchronous dynamic RAM. The loop is associated at left and/or right signal ports of the buffer devices. #CMT#USE : #/CMT# Semiconductor memory module i.e. dual inline memory module. #CMT#ADVANTAGE : #/CMT# The buffer devices are independent of each other in longitudinal direction of the printed board, and comprise separate left and right signal ports for the buffered address, command and clock signals, to transfer the signals over the unbranched signal line loop corresponding to signal ports of memory devices, thus optimizing the module and providing high memory capacity, providing mechanical stability of the module, reducing latency and current consumption while the assembly and size of the printed circuit board is flexible. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a schematic front view of a semiconductor memory module with active memory devices. 100 : Semiconductor memory module 102 : Printed board 106 : Memory devices 108 : Buffer devices 114 : Fly-by-signal line loop. |
