发明名称 IN-MEMORY, IN-PAGE DIRECTORY CACHE COHERENCY SCHEME
摘要 An in-memory and an in-page directory cache coherency technique capable of applying the increase of a processor or processor cores are provided to secure a page hit access which becomes the same as the directory cache hit. A memory access request about a cache line which is requested from one processor is received(302). A memory page storing a required cache line is brought from a memory unit. Coherency information related to the required cache line is accessed from the memory unit(304). The memory page comprises a directory line having the consistency information corresponding to the required cache line. According to the consistency information, data related to the required cache line is read(306). The data is returned by the processor(308).
申请公布号 KR20090073983(A) 申请公布日期 2009.07.03
申请号 KR20080136546 申请日期 2008.12.30
申请人 INTEL CORP. 发明人 STEINER IAN;CAI GEORGE ZHONG NING;TIWARI SAURABH;CHENG KAI
分类号 G06F13/16;G06F9/06;G06F9/46;G06F12/00 主分类号 G06F13/16
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