| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device stably executing precise operation without causing a malfunction that may occur between synchronous circuits receiving clock signals asynchronous to each other. <P>SOLUTION: An external clock generation circuit 40 generates an external clock signal T1 synchronized with a write command buffer signal TXLWE in response to a mode instruction signal RDY in an "H" level when an internal operation mode is not entered. The external clock signal T1 is fixed to an "L" level in response to entry to the internal operation mode and transition of the mode instruction signal RDY from "H" to "L". An external CUI 10 is not supplied with the external clock signal T1, and enters an external command reception prohibited state. A malfunction due to an external command input, during asynchronous reset, is avoided by keeping the mode instruction signal RDY at the "L" level until asynchronous reset is completed, and setting the signal to the "H" level after the end of asynchronous reset. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
