发明名称 |
Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry |
摘要 |
Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.
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申请公布号 |
US7555667(B1) |
申请公布日期 |
2009.06.30 |
申请号 |
US20060488365 |
申请日期 |
2006.07.17 |
申请人 |
ALTERA CORPORATION |
发明人 |
BURNEY ALI;XU YU;ZHENG LEON;CHARAGULLA SANJAY K. |
分类号 |
G06F1/04;G06F1/06 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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