| 摘要 |
A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided. The instruction executor for executing a group of instructions comprising at least one of the instructions that is included in the same string of the instructions as the detected debug instruction and allocated at an address of a lower-order position than the detected debug instruction when the debug instruction is detected by the instruction analyzer, and an instruction canceller for canceling execution of a group of instructions comprising at least one of the instructions that is included in the same string of the instructions as the detected debug instruction and allocated at an address of a higher-order position than the detected debug instruction when the debug instruction is detected by the instruction analyzer. |
