发明名称 DIGITAL BROADCAST RECEIVING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DIGITAL BROADCAST RECEIVING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To reduce a switching time without delaying the display timing. <P>SOLUTION: The digital broadcast receiving apparatus 100 includes an internal counter 107 which counts count values based on PCR; a one-seg decoding unit 105, which decodes video data of a one-seg broadcast and outputs the decoded data; a full-seg decoding unit 106 which decodes video data of a full-seg broadcast and outputs the decoded data; and a switching unit 108, which selects one of the video data output from the one-seg decoding unit 105 or the full-seg decoding unit 106 and outputs the selected data. Furthermore, each of the one-seg decoding unit 105 and the full-seg decoding unit 106 includes a clock synchronization decoding unit 201, which outputs the video data, when the video data is selected by the switching unit 108 and the difference between PTS and this counted values lies within a predetermined value, and an asynchronous decoding unit 202 which outputs the video data with timing delayed or accelerated by as much as an offset value 206, with respect to the timing of predetermined periodicity, when the video data is not selected by the switching unit 108. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009141399(A) 申请公布日期 2009.06.25
申请号 JP20070312294 申请日期 2007.12.03
申请人 PANASONIC CORP 发明人 MIYASHITA TAKANORI;TAKAYAMA SHUICHI;TATSUMOTO HIROKI
分类号 H04N7/173;H04N21/435;H04N21/438 主分类号 H04N7/173
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