发明名称 |
System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model |
摘要 |
A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge "outlier" cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
|
申请公布号 |
US7552413(B2) |
申请公布日期 |
2009.06.23 |
申请号 |
US20080166811 |
申请日期 |
2008.07.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AGARWAL VIKAS;LEE MICHAEL JU HYEOK;SHEPHARD, III PHILIP G. |
分类号 |
G06F17/50;G11C29/00 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|