Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage

摘要

A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).