| 摘要 |
A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.
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