发明名称 |
Circuit configurations to reduce snapback of a transient voltage suppressor |
摘要 |
This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
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申请公布号 |
US7538997(B2) |
申请公布日期 |
2009.05.26 |
申请号 |
US20060444555 |
申请日期 |
2006.05.31 |
申请人 |
ALPHA & OMEGA SEMICONDUCTOR, LTD. |
发明人 |
MALLIKARARJUNASWAMY SHEKAR |
分类号 |
H02H9/00 |
主分类号 |
H02H9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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