发明名称 Agile Decoder
摘要 A decoder arrangement (10) includes a processor (12) programmed to decode multiple streams (111-11n), including multiple streams of different formats. In terms of functionality, the decoder arrangement includes a routing stage (13) routes each streams to different decoder stages (141-14n), each capable of decoding a stream of a particular format to yield an uncompressed stream at its output. Each of plurality of buffer stages (161-16n) stores a successive frame of an uncompressed stream output by an associated decoder stage. An output stage scales and the frames stored by the buffer stages to a common size for input to a display device (22).
申请公布号 US2009123081(A1) 申请公布日期 2009.05.14
申请号 US20060883984 申请日期 2006.02.01
申请人 发明人 DELUCA MICHAEL ANTHONY
分类号 G06K9/36;G06K9/46 主分类号 G06K9/36
代理机构 代理人
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