发明名称 |
SIGNAL PROCESSING APPARATUS |
摘要 |
<p>The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f1 calculates (the count value ICl + the Carry + the positive integer A). The second integer counter 150 for generating the second clock f2 (f2=f1*G) calculates (the count value IC2 + the Carry + the positive integer A + the offset value) at each input clock. The correction circuit outputs the offset value so that the second integer counter counts "the maximum count value*(f2/f1-1)*D" times more than the first integer counter with respect to each cycle D having a synchronization cycle length of the first clock f1 and the second clock f2.</p> |
申请公布号 |
KR20090048348(A) |
申请公布日期 |
2009.05.13 |
申请号 |
KR20080110304 |
申请日期 |
2008.11.07 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
TSUCHIDA TOSHIYUKI;KOMATSU YOSHIKAZU |
分类号 |
H04N5/04;H04N5/05;H04N5/06;H04N5/08;H04N19/00;H04N19/44;H04N19/70 |
主分类号 |
H04N5/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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