| 摘要 |
A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time delay while the selective pin is floated or the external time delay while the selective pin is connected with a capacitor. The time delay circuit is composed of a charge-discharge circuit, a D flip-flop, a RS latch, a NOR gate, and a 2 to 1 multiplexer (MUX 2:1). According to an embodiment, if the selective pin is floated, the outputs of the D flip-flop, and the RS latch will make MUX 2:1 choose an output signal of the NOR gate having input signals of an internal delay signal and input signal. On the other hand, if the selective pin is connected with an external capacitor having an external capacitance of more than 250 pF, the output signal of the D flip-flop, and the RS latch will make MUX 2:1 choose an output of the charge-discharge circuit but ignore the internal delay signal.
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