发明名称 PATTERN DATA GENERATION METHOD, DESIGN LAYOUT GENERATING METHOD, AND PATTERN DATA VERIFYING PROGRAM
摘要 A pattern data generation method according to an example of the present invention includes based on design pattern data of a circuit including a plurality of MIS transistors having the same gate size, identifying types of the plurality of MIS transistors, setting size specs for gate patterns of the plurality of MIS transistors, the size specs being different for different types of the MIS transistors, and verifying whether gate patterns of the MIS transistors predicted by simulation using mask pattern data for forming the MIS transistors satisfy the size specs.
申请公布号 US2009119627(A1) 申请公布日期 2009.05.07
申请号 US20080252978 申请日期 2008.10.16
申请人 KONOMI KENJI 发明人 KONOMI KENJI
分类号 G06F17/50 主分类号 G06F17/50
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