发明名称 |
DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE |
摘要 |
A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.
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申请公布号 |
US2009116306(A1) |
申请公布日期 |
2009.05.07 |
申请号 |
US20080262517 |
申请日期 |
2008.10.31 |
申请人 |
HYNIX SEMICONDUCTOR, INC. |
发明人 |
SONG HEE-WOONG;PARK KUN-WOO;KIM YONG-JU;OH IC-SU;KIM HYUNG-SOO;HWANG TAE-JIN;CHOI HAE-RANG;LEE JI-WANG |
分类号 |
G11C7/00;G11C8/18;H03L7/06 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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