| 摘要 |
A semiconductor memory device is provided to improve switching speed of bit line separation transistor by securing threshold voltage. A selection control part(100) comprises an inverter(IV1, IV2), a delay unit(110), and a NAND gate(ND1). A voltage supply portion(200) comprises a PMOS transistor(P1) and an NMOS transistor(N1~N3). The NMOS transistor(N4, N5) of the bit line separate unit(300) is connected between a bit line sense AMP(BLSA) and a cell mat. The bit line separate unit receives a node through the gate terminal, and the bit line sense AMP senses and amplifies data of the cell mat. The cell mat comprises a plurality of memory cells selected by a plurality of bit lines with a plurality of word lines. |
