| 摘要 |
<p>The method involves stacking wafers (1) to superimpose zones of curved segments e.g. circle arc, of electrical connection tracks. Vias are pierced in an insulating resin along a direction of the stacking, and directly above spaces that are surrounded by the zones to form the vias. A wall of the vias is metallized by electrolytic growth. The stacking of the wafers is cut along cutting paths to form three-dimensional electronic modules, where the width of the cut of stacking is higher than the width of an electrode interconnecting the tracks.</p> |
