发明名称 Circuit-level memory and combinational block modeling
摘要 A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
申请公布号 US7516060(B2) 申请公布日期 2009.04.07
申请号 US20050225932 申请日期 2005.09.13
申请人 AVERANT, INC. 发明人 ISLES ADRIAN J.
分类号 G06F7/60;G06F9/45;G06F17/50;G06G7/62 主分类号 G06F7/60
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