Filter-based lock-in circuits for PLL and fast system startup

摘要

All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower transistor have a shared source (or drain) terminal which becomes a single bidirectional node. They further comprise a sensing gate and a logic gate. The sensing inverter has a function of sensing a voltage at the single bidirectional node and comparing it with an input transition voltage since an input terminal of the sensing inverter is connected to the single bidirectional node. An initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter, where the input transition voltage is an input voltage which causes an output voltage to be $\frac{V_{\mathrm{DD}}}{2}.$ Consequently, all embodiments of the present invention provide a fast lock-in time performance and achieve a drastic improvement in system startup time, system latency time, system simulation time, system test time, cost, and time to market