| 摘要 |
Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1, and <o ostyle="single">D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and <o ostyle="single">R1). The second differential output unit receives NRZ input signals (D2 and <o ostyle="single">D2) and an inverted clock signal ( <o ostyle="single">CLK), and generates differential RZ-mode outputs (R2 and <o ostyle="single">R2). The selection unit receives the RZ-mode output signals (R1, <o ostyle="single">R1, R2, and <o ostyle="single">R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).
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