| 摘要 |
A data line driving circuit includes a plurality of blocks that are cascaded together, wherein each of the plurality of blocks includes a shift register that sequentially outputs a plurality of selection signals for each block in synchronization with a clock signal; a data synchronization circuit that adjusts a phase of a data signal in which a plurality of items of data are arranged chronologically by using the clock signal as a reference and to output the data signal to a block of the next stage; a data expansion circuit that expands the items of data of the data signal after being adjusted by the data synchronization circuit into a plurality of systems on the basis of the plurality of selection signals; and a signal generation circuit that generates a driving signal corresponding to each item of data after being expanded by the data expansion circuit.
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