| 摘要 |
The invention provides chip designers a means to take advantage of ANoC interconnect, the combination of the two technologies, asynchronous circuits and Network on Chip (ANoC), enabling them to design large chips more easily and quickly than before. The designer develops a table of interconnect requirements, specifying the desired connections and certain constraints such as area, power, and latency. The invention develops a connectivity network utilizing a library of characterized components, then optimizes the network by selecting various alternative components from the library and examining alternative link width combinations. The optimized network is verified against the predetermined requirements. If the verification is successful a fabric file is provided. If the verification is not successful the optimization process is repeated provided some improvement has been made.
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