发明名称 |
APPARATUS AND METHOD FOR VITERBI DECODING |
摘要 |
An apparatus and a method for viterbi decoding are provided to increase an operation speed by using a block processing decoding method. A viterbi decoder includes a distributor(281), a plurality of memory banks(283a-283h), a plurality of switches(285a-285h) and a plurality of decoding units(287a,287b). The distributor distributes the plurality of bits inputted from the de-puncturer in a block data unit. The plurality of memory banks store the block data inputted from the distributor. The plurality of switches are connected to the plurality of memory banks respectively. Each switch outputs block data stored in one memory bank. Each decoding unit is connected to a part of switches. Each decoding unit performs the viterbi decoding algorithm about block data and outputs a part of block data.
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申请公布号 |
KR100888508(B1) |
申请公布日期 |
2009.03.12 |
申请号 |
KR20070130384 |
申请日期 |
2007.12.13 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
CHOI, SUNG WOO;KANG, KYU MIN;CHOI, SANG SUNG;PARK, KWANG ROH |
分类号 |
H03M13/41 |
主分类号 |
H03M13/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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