| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a read error is not caused even when the voltage of a cell source line is raised, and high speed sense operation can be performed. <P>SOLUTION: In a memory cell array 1, a plurality of control areas CA are formed in the direction orthogonal to the direction of extension of a bit line. In a sense amplifier 3, initial charging is performed for bit lines BL in respective control areas of the memory cell array 1 by a charge voltage controlled by respective individual bit line control signals BLC. A plurality of BLC generating circuits 4 are provided correspondingly to respective control areas CA of the memory cell array 1, each of BLC generating circuits inputs the potential of a cell source line CELSRC in a corresponding control area, then individually generates and outputs the bit line control signal BLC in each control area in accordance with input voltage of the cell source line CELSRC in each control area. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
