发明名称 |
Method, apparatus and system for facilitating debug for link interconnects |
摘要 |
A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.
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申请公布号 |
US7496801(B2) |
申请公布日期 |
2009.02.24 |
申请号 |
US20050167965 |
申请日期 |
2005.06.27 |
申请人 |
INTEL CORPORATION |
发明人 |
GLASS RICHARD J.;ATHREYA MADHU S.;DRESCHER KEITH A.;DESAI PIYUSH |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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