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发明名称
Level limiting emitter biasing circuit for preventing complete cut-off of transistor
摘要
申请公布号
US3041471(A)
申请公布日期
1962.06.26
申请号
US19600044202
申请日期
1960.07.20
申请人
COMPAGNIE DES MACHINES BULL
发明人
FEISSEL HENRI GERARD
分类号
H03K3/281
主分类号
H03K3/281
代理机构
代理人
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