CIRCUIT FOR GENERATING CLOCK OF SEMICONDUCTOR MEMORY APPARATUS

摘要

A clock generation circuit of a semiconductor memory device is provided to prevent an error of transition timing of a rising clock and a falling clock due to a change of P.V.T(Process Voltage Temperature) and a transmission distance. A clock generation circuit of a semiconductor memory device includes a phase splitter(100) and a clock buffer(200). The phase splitter delays a clock(CLK) and generates a delayed clock(CLK_d). The phase splitter generates an inverted clock(CLK_b) by inverting the clock. The clock buffer outputs a rising clock(RCLK) and a falling clock(FCLK) by buffering the delayed clock and the inverted clock.