| 摘要 |
An apparatus and for preventing a glitch in a clock switching circuit includes a select signal manager and a clock gate unit. The select signal manager generates a detect change signal, provides the detect change signal as an input signal for generating a clock gate signal to the clock gate unit, and changes a muxsel signal into a select signal using the clock gate signal to select a clock intending for switching. Upon receiving the detect change signal, the clock gate unit gates a received clock, generates the clock gate signal using a level of the detect change signal as an input signal, and provides the generated clock gate signal to the select signal manager.
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