发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND REDUNDANCY METHOD THEREOF
摘要 A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.
申请公布号 US2009044045(A1) 申请公布日期 2009.02.12
申请号 US20080186899 申请日期 2008.08.06
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KOHARA KOJI;HOJO TAKEHIKO
分类号 G06F11/20 主分类号 G06F11/20
代理机构 代理人
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