发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a delay penalty of an output signal of a power source noise resistance evaluation object circuit generated from a driving circuit connected to the subsequent stage of the power source noise resistance evaluation object circuit, caused by an influence of a power source noise generated from a power source noise generation circuit, and evaluating highly accurately the power source noise resistance of the power source noise resistance evaluation object circuit. SOLUTION: This device is loaded with the power source noise resistance evaluation object circuit 26, the driving circuit 28 connected to the subsequent stage of the power source noise resistance evaluation object circuit 26, and the power source noise generation circuit 27 for generating the power source noise. The device is also loaded with a delay penalty compensation circuit 34 for reducing the delay penalty generated in the driving circuit 28 caused by the influence of the power source noise generated from the power source noise generation circuit 27. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009025072(A) 申请公布日期 2009.02.05
申请号 JP20070186664 申请日期 2007.07.18
申请人 FUJITSU LTD 发明人 SASAGAWA RYUHEI
分类号 G01R31/30;G01R29/26;G01R31/28 主分类号 G01R31/30
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