| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit which can generate an output clock signal synchronized with an input signal while appropriately correcting deviation of an output clock signal caused by missing of an input signal. <P>SOLUTION: The clock generating circuit 10 which generates the output clock signal by multiplying an input signal having the prescribed frequency by a prescribed multiplication ratio is provided. This clock generating circuit 10 is provided with a PLL circuit 100 for generating the output clock signal by multiplying the input signal, and a correction circuit 20 for changing the multiplication ratio of the PLL circuit 100, wherein the correction circuit 200 changes the multiplication ratio of the PLL circuit 100 from the prescribed multiplication ration to a multiplication ratio in which the prescribed multiplication ratio is increased or decreased only during a correction section for each correction period longer than one period of the input signal so that time difference between an input synchronization signal synchronized with the input signal and an output synchronization signal synchronized with the output clock signal can be reduced, and the PLL circuit 100 multiplies the input signal by a changed multiplication ratio in the correction section. <P>COPYRIGHT: (C)2009,JPO&INPIT |
