<p>In a memory circuit region (Z2) of a silicon substrate (1), a memory cell comprising a memory cell transistor (QM) and a resistive element (RM) is formed. In a testing region (Z3), a resistive element for testing (RMT) is formed. The resistive element (RM) and the resistive element for testing (RMT) both have the same structure including a memory layer (36) comprising a phase-change material. To each of an upper electrode (37) and a lower electrode (33) of the resistive element for testing (RMT), a bonding pad for testing is electrically connected.</p>
