发明名称 Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification
摘要 Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set. Advantageously, the laborious and error-prone process of manually determining the proper inputs to apply during formal verification is avoided.
申请公布号 US7475369(B1) 申请公布日期 2009.01.06
申请号 US20050083805 申请日期 2005.03.18
申请人 SUN MICROSYSTEMS, INC. 发明人 LAM WILLIAM K.;MEHTA SHRENIK M.
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
代理机构 代理人
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