发明名称 |
Mechanism to generate logically dedicated read and write channels in a memory controller |
摘要 |
According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot. |
申请公布号 |
GB2442346(B) |
申请公布日期 |
2008.12.17 |
申请号 |
GB20070018968 |
申请日期 |
2007.09.27 |
申请人 |
INTEL CORPORATION |
发明人 |
RAMESH SUBASHCHANDRABOSE;ANUPAM MOHANTY;RAJAT AGARWAL |
分类号 |
G06F13/16;G11C7/10;G11C11/409 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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