发明名称 INTERFACE CIRCUIT WITH TRANSISTOR-TRANSISTOR LOGIC LEVEL
摘要 PURPOSE:To lower the threshold level without increasing the channel width of an N type MOSEFT, by using an inverter no doped with impurity to a channel of a P type MOSFET. CONSTITUTION:A P type impurity is doped to a channel 101 of an N channel MOSFET formed on a P type impurity diffusion region 107, and the P type impurity is not doped to a channel section 201 of a P channel MOSFET. Thus, the threshold voltage of the P channel MOSFET can be decreased, and when it is used for an interface circuit from TTL level to CMOSes, the threshold voltage of the inverter can be lowered to 1.4V taking maximum noise margin, without increasing the channel width of the N channel MOSFET.
申请公布号 JPS5799038(A) 申请公布日期 1982.06.19
申请号 JP19800175595 申请日期 1980.12.12
申请人 SUWA SEIKOSHA KK 发明人 MIYAZAKI NOBUYUKI;ODA ZENZOU
分类号 H01L21/331;H01L21/8238;H01L27/092;H01L29/73;H03K19/018 主分类号 H01L21/331
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