| 摘要 |
PURPOSE:To prevent the formation of parasitic transistors and cut down the chip size, by a method wherein a resistor region and the base and emitter region of a transistor are provided in an island region isolated electrically and the base region is surrounded by a region of the same conductive type as the island region but high impurities concentration. CONSTITUTION:Transistor elements Q1 and Q2 are provided which are parallel- connected between the terminal of a power supply terminal (1) and a ground terminal (2), and each collector is connected with said terminal (1) and each emitter with the terminal (2) through respective resistors R3 and R4. The emitter of the element Q1 is connected with the base of the element Q2. Resistors R1 and R2 are provided in parallel with these circuits, and the neutral is connected with the base of the element Q1. In such IC, an N<+> type maximum bias potential supply region (4) mounted on the semiconductor substrate is rendered to combine the collector regions of the elements Q1 and Q2 and render it the higher impurity concentration than an N<-> type epitaxial layer (3) in existance of the resistor. In such a case, the base regions (6) and (16) of the elements Q1 and Q2 are surrounded by the region (4') to prevent the occurrence of parasitic effect. |
