发明名称 |
Dynamic memory with improved arrangement for precharging bit lines |
摘要 |
A dynamic memory which can accurately precharge a pair of bit lines to a potential equal to half the power supply voltage and which has improved detection characteristics is disclosed. The dynamic memory is of the type in which a precharge potential of a pair of bit lines is generated by short-circuiting the pair of bit lines after the pair of bit lines are discriminated into the power supply voltage and the reference voltage (ground). A compensation capacitor is provided for the pair of bit lines. The compensation capacitor is charged to the power supply voltage and the charged compensation capacitor is operatively connected to the pair of bit lines when they are short-circuited to thereby raise the potential on the bit lines to half the power supply voltage.
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申请公布号 |
US4733373(A) |
申请公布日期 |
1988.03.22 |
申请号 |
US19860824030 |
申请日期 |
1986.01.30 |
申请人 |
NEC CORPORATION |
发明人 |
MUROTANI, TATSUNORI |
分类号 |
G11C11/409;G11C11/4094;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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