发明名称 TROUBLE PROCESSING SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To prevent such double trouble that an input/output controller becomes faulty when waiting for an answer from a central processor by stopping the input/ output controller by a service processor in case of the trouble of the central processor and restarting the input/output controller when the central processor retries processing successfully. CONSTITUTION:An interruption accepting circuit 20 in the service processor 2 accepts an interruption from a trouble informing circuit 11 and a state read circuit 21 sends a polling signal to a state display circuit 13 to read the result of the retrial processing of the central processor 1. Then a start/stop control circuit 22 resets the central processor 1 when the interruption accepting circuit 20 accepts the interruption, to perform the retrial processing of the central processor 1 by a CPU retrial processing circuit 12. Simultaneously, input/output controllers 3 and 4 are stopped from operating and when the state read circuit 21 reads out the retrial success as the result of the retrial processing of the central processor 1, the retrial processing of the input/output controllers 3 and 4 is performed by IOP retrial processing circuits 30 and 31. Consequently, such double trouble that when the central processor becomes faulty, the input/ output controllers also become faulty at the time of waiting an answer from the central processor is prevented.
申请公布号 JPH01314340(A) 申请公布日期 1989.12.19
申请号 JP19880147126 申请日期 1988.06.14
申请人 NEC CORP 发明人 CHINJU MASAAKI
分类号 G06F11/14 主分类号 G06F11/14
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