| 摘要 |
PURPOSE:To degrade only an address in which a parity error is detected and to improve the performance of a cache in the cache divided into several compartments. CONSTITUTION:When parity error circuits 4 and 5 detects the parity error in data 102 and 103 from cache 2 and 3, degrading information is stored in error generation registers 6 and 7 for each address in the caches 2 and 3. At the time of registration of new data, the cache to be used for registering the new data is determined by a assigned compartment determination circuit 10 based on degrading information 106 and 107 from the error generation registers 6 and 7 which are corresponding to the writing address of the data as well as based on an access history 109 form a compartment access history storage buffer 9. |
