| 摘要 |
A circuit and a method for limiting a signal voltage are provided to decrease a signal interference in a signal processor by restricting a signal voltage upstream of a process stage. An input unit receives an input signal. An output unit(20) outputs an output signal to a process stage. A VL(Voltage Limiting circuit) is connected to the input and output units and receives the input signal. When the input signal is lower than a maximum voltage, the VL outputs the output signal to be proportional to the input voltage. When the input signal is higher than the maximum voltage, the VL outputs a constant output signal. The VL includes a voltage divider and a differential amplifier. The voltage divider includes at least one voltage divider component. The different amplifier amplifiers a difference between the output signal and a reference voltage and outputs the output signal as a control signal to the voltage divider component.
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