| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock changing circuit which securely makes clock change between a one multiplied clock and a predetermined multiplied clock. <P>SOLUTION: In the clock changing circuit, odd-numbered and even-numbered routes are alternatively and selectively controlled to be subjected to parallel/serial conversion with a one multiplied definer signal (×)DEF synchronized with a two multiplied clock CLK (×2) to securely change a one multiplied clock CLK (×1) of two routes to a two multiplied clock (×2) of one route. Further, even-numbered and odd-numbered serial (1, 2, 3, and 4) scan data are changed to the one multiplied clock CLK (×1) after the definer signal DEF and two multiplied clock CLK (×2) are temporarily converted with a clock CLK (×1) passed through a NOR circuit 36, and the scan data are securely reproduced while skew is taken into consideration when the two multiplied clock of one route is put back into the one multiplied CLK (×1) of two routes. <P>COPYRIGHT: (C)2009,JPO&INPIT |
