| 摘要 |
A signal selecting circuit and a semiconductor memory device including the same are provided to reduce loading of an output stage even though a signal is selected among a number of signals. A plurality of first selection parts(411,412,413) select an output enable signal proper for CAS latency among a number of output enable signals with different timing. A second selection part(430) selects an output proper for CAS latency among outputs of the first selection parts. A latch part(420) latches more than one of the outputs of the first selection parts and outputs them to the second selection part.
|
