METHOD AND APPARATUS FOR ELIMINATING CLOCK JITTER IN CONTINUOUS-TIME DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS

摘要

An inventive high-resolution Delta-Sigma analog-to-digital converter (15) using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter (17) that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter (17) preferably includes at least two switches and a capacitor (28).