| 摘要 |
PROBLEM TO BE SOLVED: To solve a problem with conventional parallel AD converters in which the number of comparators increases exponentially with an increase in the number of bits, leading to an increase in power consumption and chip area or a decrease in operating speed of an encoding circuit and an increase in power during a precharge operation. SOLUTION: A plurality of reference voltages Vr1 to Vr15 obtained by voltage division by resistors R1 to R16 are put into paired groups. The reference voltages of each group are referred to as a first and a second reference voltage. Comparators 11-1 to 11-8 each of which has a function of determining a binary value and outputs a determination result only when an analog input signal is within the first and second reference voltages, are used to calculate the logical OR of the outputs of the odd-numbered comparators 11-1, 11-3, 11-5 and 11-7 using an OR circuit 12 and calculate the logical OR of the outputs of the even-numbered comparators 11-2 and 11-6 using an OR circuit 13. Thereby, the outputs of the OR circuits 12 and 13 and the outputs of the comparators 11-4 and 11-8 are each a gray code. This is converted into a binary code, i.e., a digital signal by a code conversion circuit 14. COPYRIGHT: (C)2008,JPO&INPIT
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