发明名称 |
VERPACKUNG AUF WAFEREBENE FÜR MIKROELEKTROMECHANISCHE VORRICHTUNGEN |
摘要 |
A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing a metal layer on one of a first wafer and a second wafer; bonding the first wafer and the second wafer using the metal layer deposited on one of the first wafer and the second wafer; forming a through-wafer via in one of the first wafer and the second wafer; filling the through-wafer via with a conductive material; and forming a cavity in the one of the first wafer and the second wafer having the through-wafer via, wherein the cavity is superposable over a device. <IMAGE> |
申请公布号 |
AT396955(T) |
申请公布日期 |
2008.06.15 |
申请号 |
AT20030256508T |
申请日期 |
2003.10.15 |
申请人 |
INSTITUTE OF MICROELECTRONICS |
发明人 |
NAGARAJAN, RANGANATHAN;PREMACHANDRAN, C. S.;CHEN, YU;KRIPESH, VAIDYANATHAN |
分类号 |
B81B7/00 |
主分类号 |
B81B7/00 |
代理机构 |
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地址 |
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