| 摘要 |
PROBLEM TO BE SOLVED: To secure the reliability of both of two writing wirings by optimizing the structure of a memory cell. SOLUTION: The wiring width and thickness of a pit line 10 are shown by W1 and T1, the thickness of a digit line 5 is shown by T2, and a distance between a center in the thickness direction of the digit line 5 and a center in the thickness direction of a free layer for an MTJ element 8 is shown by L1. The wiring width of the digit line 5 is shown by W2 and a distance between a center in the thickness direction of the bit line 10 and the center in the thickness direction of the free layer for the MTJ element 8 is shown by L2. In this case, the distances L1, L2 and the sectional areas of the wirings S1, S2 are set so as to satisfy (1/3)×(L1/L2)≤S2/S1≤1 when L1/L2≥1 or satisfy 1≤S2/S1≤3(L1/L2) when L1/L2≤1. COPYRIGHT: (C)2006,JPO&NCIPI
|
