| 摘要 |
PROBLEM TO BE SOLVED: To efficiently perform CPU and DSP data processing and data transfer by DMA in a parallel fashion. SOLUTION: A DMA control circuit 5 has a total-register-length register 5-1 and a transfer-length register 5-2. Once the DMA transfer of data for the length of transfer set in the transfer-length register 5-2 is achieved, the transfer is temporarily stopped. When resumption is instructed, the transfer is resumed. Once all the data transferred have reached the transfer length set in the total-transfer-length register 5-1, the DMA transfer is terminated. COPYRIGHT: (C)2006,JPO&NCIPI
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