发明名称 Gated clock logic circuit
摘要 A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.
申请公布号 US2006097754(A1) 申请公布日期 2006.05.11
申请号 US20050266659 申请日期 2005.11.02
申请人 KIM MIN-SU 发明人 KIM MIN-SU
分类号 H03K19/096;G06F1/04 主分类号 H03K19/096
代理机构 代理人
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