发明名称 |
Method of associating timing violations with critical structures in an integrated circuit design |
摘要 |
A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.
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申请公布号 |
US2006101363(A1) |
申请公布日期 |
2006.05.11 |
申请号 |
US20040984115 |
申请日期 |
2004.11.08 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
FRY RANDALL P.;PIERCE GREGORY;LAHNER JUERGEN |
分类号 |
G06F17/50;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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